Synopsys Timing Constraints And Optimization User Guide Instant

A design failing timing by 20% on a multiplier. Without retiming, the tool tries to upsize, increasing area by 40%. With compile_ultra -retime , the tool redistributes the logic, meeting timing with only 5% area increase.

The chip doesn't live in a vacuum. You must tell the tool how much time the "outside world" consumes. Synopsys Timing Constraints And Optimization User Guide

Not all paths are equal. The User Guide introduces set_critical_range and set_cost_priority . A design failing timing by 20% on a multiplier