The revised edition (March 2016) is widely available through academic and commercial retailers:
One unique chapter walks the reader through writing a Verification Plan (aka "Verification Spec"). This is a document that lists every feature of the design and how it will be tested. Thomas provides templates for: The revised edition (March 2016) is widely available
Then there is the rare third camp:
Donald Thomas is a veteran in the field of Electronic Design Automation (EDA). His name is synonymous with the classic text The Verilog Hardware Description Language , which he co-authored. This legacy gives him a unique vantage point. He is not a new author jumping on the SystemVerilog bandwagon; he is an educator who has watched the language evolve from its roots. His name is synonymous with the classic text
This is precisely the gap that aims to bridge. As one of the definitive textbooks on the subject, this book does not merely teach a Hardware Description Language (HDL); it teaches a mindset. It treats design and verification not as separate silos, but as intertwined disciplines essential for modern System-on-Chip (SoC) development. This is precisely the gap that aims to bridge