Tsmc Technology Symposium 2012 Pdf !!link!! File

This is the most controversial section of the . TSMC presented 20nm as a "half-node" that offered 1.9x gate density and 25% speed gain over 28nm, but critically— without FinFETs. History proved 20nm had a short life (only used in Apple’s A8 and a few GPUs), but the 2012 PDF shows TSMC’s rationale: 20nm was a necessary lithography and double-patterning training ground for 16nm.

The qualification of 65nm embedded flash for automotive use and the release of 0.5μm ultra-high voltage power IC technology. Tsmc Technology Symposium 2012 Pdf

The 2012 PDF contains one of the first public acknowledgements that 20nm and 16nm would require double patterning for metal layers. The slide titled "Lithography Transition" shows mask cost increases from $1M (28nm) to $3M (20nm). This was the industry's first shock at EUV’s delay, a theme that continues with high-NA EUV costs in 2024. This is the most controversial section of the

The PDF includes actual ring oscillator speeds: 28HPM delivered a 30% speed improvement over 40nm at the same leakage current. For competitive analysts, these numbers provided a benchmark against GlobalFoundries’ 28nm SLP and Samsung’s 28nm LP. The qualification of 65nm embedded flash for automotive

The most sought-after slides in the PDF concern TSMC’s first generation of 3D transistors. At the 2012 symposium, TSMC revealed that its FinFET would debut at 16nm (not 20nm). Key data points in the PDF include: