__top__ | 8-bit Microprocessor Verilog Code

endmodule

The carry, result = a + b syntax creates an adder with a carry-out bit. Most modern FPGAs will map this efficiently to dedicated carry chains. 8-bit microprocessor verilog code

// Instantiate ALU alu alu_inst ( .a(acc_data), .b(x_data), .alu_sel(alu_op), .result(alu_out), .zero(alu_zero_flag), .carry() ); endmodule The carry, result = a + b

module processor_tb; reg clk, rst; wire [15:0] addr; wire [7:0] data; wire mem_read, mem_write; processor uut (.clk(clk), .rst(rst), .addr_bus(addr), .data_bus(data), .mem_read(mem_read), .mem_write(mem_write)); endmodule The carry

module control_unit ( input wire clk, rst_n, input wire [7:0] opcode, input wire alu_zero, output reg reg_write, output reg [1:0] reg_sel, output reg [2:0] alu_sel, output reg pc_jump, output reg [15:0] jump_target, output reg mem_write, output reg halt );

always @(posedge clk or posedge rst) begin if (rst) begin registers[0] <= 8'h00; registers[1] <= 8'h00; registers[2] <= 8'h00; registers[3] <= 8'h00; end else if (wr_en) begin registers[reg_sel_wr] <= wr_data; end end