Clock Divider Verilog 50 Mhz 1hz Portable

EGC221: Digital Logic Lab - Division of Engineering Programs

module clk_div_toggle ( input wire clk_50M, input wire rst_n, output reg clk_1Hz ); localparam MAX_COUNT = 25_000_000; // Half period count reg [24:0] counter; reg toggle; clock divider verilog 50 mhz 1hz

: Using an undersized counter is a common error. Ensure your register has enough bits (at least 25 bits for 25 million) to prevent premature rollover. EGC221: Digital Logic Lab - Division of Engineering

`timescale 1ns / 1ps

// Wait for a few toggles // With